FPGA subsystem

RTL Engineer – DMA Subsystem (FPGA / Verilator Simulation)

Overview
Seeking an experienced RTL engineer to implement and verify a DMA (Direct Memory Access) controller for a custom FPGA-based system.
All registers, addresses, and timing are fully defined in the provided design packets.

Scope of Work
- Implement the DMA controller in SystemVerilog or Verilog per the provided register map and simulation contract.
- The design must comply with the shared 16-bit synchronous bus interface and READY-based handshake timing.
- Provide a self-contained Verilator simulation that demonstrates:
- Basic data transfers
- IRQ behavior (DONE / ERROR)
- Correct handling of LEN=0 and ABORT conditions

Files Provided
- DMA design packet (dma_registers.yaml, supporting documentation)
- Shared bus and arbitration specification
- DMA Simulation Addendum Kit (contract, testbench, RAM model, Verilator scripts)

Deliverables
- dma_core.sv (synthesizable RTL)
- Simulation PASS output under Verilator
- Short README explaining architecture and any assumptions

Tools
- Verilator for simulation
- Code must be synthesizable for Lattice ECP5-class FPGAs

Acceptance Criteria
- Supplied testbench runs cleanly in Verilator and passes both included tests
- RTL matches all register addresses, bitfields, and timing in documentation

Ownership
All source code and deliverables become the property of the client upon payment.