FPGA acceleration for optimized DNN -- 2

I am interested to work on a long term research project where I need to conduct a depth study to find a new robust method (Approach) in the area of FPGA acceleration with Deep Learning optimization with the skills of HW/SW Co-design for either memory optimization, algorithm optimization, Modification of architecture, deep compression using pruning and quantization, etc. My prefer FPGA is Xilinx Ultrascale which is going to be programmed using HLS, and I am open for any Neural Network that is good to be researched.