FPGA-Controlled Precision Current Source Project
Budget: $250 – $750 USD
I need a complete design for a constant-current driver that can source or sink programmable currents through five pairs of output pins, all of which must be able to change magnitude or polarity at the exact same instant when commanded. Target currents are in the single-milliamp range and the entire system must hold ±0.1 % accuracy over normal laboratory temperature conditions.
The digital heart of the design will be a Xilinx FPGA. Around it I want to use a precision analog front-end built from the following building blocks:
• Operational Amplifiers (Op-Amps)
• Digital-to-Analog Converters (DACs)
• A Howland Current Pump topology
If you have a more elegant approach that still meets the accuracy requirement I’m open to hearing it, but the solution must remain feasible for small-batch assembly.
Deliverables
• Complete walkthrough of how to connect components to FPGA
• Verilog/VHDL code for the FPGA, including a simple register map that lets a microcontroller or PC set each channel’s current (positive or negative) and trigger synchronous updates.
• Well-commented simulation files showing stability of the analog loop and timing closure in the FPGA.
I will provide the desired mechanical outline for the board and the mA ranges per channel once we start. Your expertise in precision analog layout, Xilinx tool chain (Vivado), and mixed-signal debugging will be critical to getting this right the first time.
The digital heart of the design will be a Xilinx FPGA. Around it I want to use a precision analog front-end built from the following building blocks:
• Operational Amplifiers (Op-Amps)
• Digital-to-Analog Converters (DACs)
• A Howland Current Pump topology
If you have a more elegant approach that still meets the accuracy requirement I’m open to hearing it, but the solution must remain feasible for small-batch assembly.
Deliverables
• Complete walkthrough of how to connect components to FPGA
• Verilog/VHDL code for the FPGA, including a simple register map that lets a microcontroller or PC set each channel’s current (positive or negative) and trigger synchronous updates.
• Well-commented simulation files showing stability of the analog loop and timing closure in the FPGA.
I will provide the desired mechanical outline for the board and the mA ranges per channel once we start. Your expertise in precision analog layout, Xilinx tool chain (Vivado), and mixed-signal debugging will be critical to getting this right the first time.