FPGA/ASIC Bitcoin Vanity Generator

I already rely on Jean-Luc Pons’s open-source VanitySearch (C/CUDA) to grind private keys on GPUs, but I now need the exact same pipeline in hardware. The goal is an RTL design that can be prototyped on modern FPGAs and, once proven, migrated to an ASIC.

Target specification
• ≥ 4 billion secp256k1 keys per second per board (for user defined compressed & uncompressed; SegWit P2WPKH optional but preferred).
• Full on-board scalar multiplication, SHA-256, RIPEMD-160 and address formatting; only matching results are returned to the host.
• Host API: startKey, stride, iterations, Bloom/filter blob → receive hits.
• Continuous 24 / 7 operation below 150 W per board.

What I need from you
Submit a detailed project proposal that confirms feasibility, sketches the architecture (parallel engines, expected clock, resource use), names the FPGA family you would prototype on, and projects the ASIC performance and die size. Include milestones, cost and a timeline that lets us enter hardware testing within one month. Prior crypto-acceleration or high-speed ECC work is highly relevant, so highlight it briefly.

Deliverables
1. Synthesizable RTL (Verilog or VHDL) covering ECC, hashing and filter logic
2. Reference bitstream for the chosen evaluation board plus host-side control script
3. Testbench & vectors proving functional correctness against VanitySearch outputs
4. Performance/power report demonstrating that the design meets or exceeds the stated targets

I’m ready to start immediately and will respond quickly to clarifying questions. Looking forward to your proposal.