Expert FPGA/SDR Engineer for ADRV9009+ZC706 System
Budget: $25 – $50 USD
FPGA + SDR (ADRV9009) System Development – ZC706 Platform
Project Description
We are looking for an experienced FPGA / SDR engineer to develop a complete ADRV9009 + Xilinx ZC706 based SDR system.
The project includes RX/TX signal processing, FPGA firmware development, Linux integration, and Ethernet-based control and data streaming.
Hardware Platform
• FPGA Board: Xilinx ZC706 Evaluation Board
• RF Front-End: Analog Devices ADRV9009 SDR Development Board
• System Type: Single integrated ADRV9009 + FPGA SDR system
Interfaces
• JESD204 (ADRV9009 - FPGA)
• Ethernet (ARM/FPGA - PC)
RX (Receiver) Requirements
• Capture RF signals with 200 MHz instantaneous bandwidth
• Configurable parameters:
• Center frequency
• Bandwidth
• Sensitivity
• ADRV9009 wideband RX configuration
• JESD204B RX data path into FPGA
• DMA-based streaming to DDR (ZC706)
• Ethernet streaming of RX data to PC
• Remote configuration via Ethernet
TX (Transmitter) Requirements
• RF signal generation at 450 MHz
• Frequency sweep capability
• Configurable parameters:
• Bandwidth
• Output power
• Frequency range
• FPGA-based waveform generation or DMA-fed TX data
• ADRV9009 TX configuration via SPI/API
• Runtime frequency sweep and parameter updates
• Ethernet-based real-time control
Control & Software
• Linux running on ZC706 ARM (PS)
• Ethernet-based control interface (TCP/UDP, to be defined)
• Centralised control of:
• ADRV9009 RF parameters
• JESD204 and data-path configuration
• RX/TX runtime behaviour
Deliverables
• FPGA firmware
• Vivado project files
• HDL source code
• JESD204 configuration
• Linux-side components and drivers (if required)
• Ethernet control interface implementation
• PC-side control protocol documentation
• Optional reference scripts or test applications
• Full technical documentation:
• System architecture overview
• Build and deployment guide
Required Skills
• Xilinx FPGA development (Vivado, HDL)
• JESD204 (B/C)
• Analog Devices ADRV9009 / SDR platforms
• Embedded Linux on Zynq (ARM)
• High-speed data streaming (DMA, Ethernet)
• RF systems and signal processing
Project Type
• Fixed-price or hourly (to be discussed)
• Remote work
• NDA may be required
Project Description
We are looking for an experienced FPGA / SDR engineer to develop a complete ADRV9009 + Xilinx ZC706 based SDR system.
The project includes RX/TX signal processing, FPGA firmware development, Linux integration, and Ethernet-based control and data streaming.
Hardware Platform
• FPGA Board: Xilinx ZC706 Evaluation Board
• RF Front-End: Analog Devices ADRV9009 SDR Development Board
• System Type: Single integrated ADRV9009 + FPGA SDR system
Interfaces
• JESD204 (ADRV9009 - FPGA)
• Ethernet (ARM/FPGA - PC)
RX (Receiver) Requirements
• Capture RF signals with 200 MHz instantaneous bandwidth
• Configurable parameters:
• Center frequency
• Bandwidth
• Sensitivity
• ADRV9009 wideband RX configuration
• JESD204B RX data path into FPGA
• DMA-based streaming to DDR (ZC706)
• Ethernet streaming of RX data to PC
• Remote configuration via Ethernet
TX (Transmitter) Requirements
• RF signal generation at 450 MHz
• Frequency sweep capability
• Configurable parameters:
• Bandwidth
• Output power
• Frequency range
• FPGA-based waveform generation or DMA-fed TX data
• ADRV9009 TX configuration via SPI/API
• Runtime frequency sweep and parameter updates
• Ethernet-based real-time control
Control & Software
• Linux running on ZC706 ARM (PS)
• Ethernet-based control interface (TCP/UDP, to be defined)
• Centralised control of:
• ADRV9009 RF parameters
• JESD204 and data-path configuration
• RX/TX runtime behaviour
Deliverables
• FPGA firmware
• Vivado project files
• HDL source code
• JESD204 configuration
• Linux-side components and drivers (if required)
• Ethernet control interface implementation
• PC-side control protocol documentation
• Optional reference scripts or test applications
• Full technical documentation:
• System architecture overview
• Build and deployment guide
Required Skills
• Xilinx FPGA development (Vivado, HDL)
• JESD204 (B/C)
• Analog Devices ADRV9009 / SDR platforms
• Embedded Linux on Zynq (ARM)
• High-speed data streaming (DMA, Ethernet)
• RF systems and signal processing
Project Type
• Fixed-price or hourly (to be discussed)
• Remote work
• NDA may be required