Educational 8-bit FPGA CPU Design
Budget: $30 – $250 USD
Note: The project must include code, schematics, and a short technical write‑up.
● Design a basic CPU (even 8‑bit or a minimal RISC‑V subset) in Verilog/VHDL,
implement it on a low‑cost FPGA board, and run a small instruction set or demo
program, emphasizing microarchitecture choices and timing closure.
● Deliverables: HDL source, timing/area reports, simulation testbenches, and a brief
report on design methodology and verification strategy.
● Mixed‑signal sensor acquisition front‑end
Note: The project must include code, schematics, and a short technical write‑up.
● Design a basic CPU (even 8‑bit or a minimal RISC‑V subset) in Verilog/VHDL,
implement it on a low‑cost FPGA board, and run a small instruction set or demo
program, emphasizing microarchitecture choices and timing closure.
● Deliverables: HDL source, timing/area reports, simulation testbenches, and a brief
report on design methodology and verification strategy.
● Mixed‑signal sensor acquisition front‑end
Note: The project must include code, schematics, and a short technical write‑up.