3-Bit Counter on Zynq
Budget: ₹600 – ₹1,500 INR
I’m looking for a clean Verilog design that realises a 3-bit synchronous counter, counts in ordinary binary from 0 through 7, and drives a single seven-segment display mounted on a Zynq MP FPGA board. Everything will be built and programmed inside Xilinx Vivado, so please target the standard Zynq MPSoC constraints and make sure your files open and synthesise without warnings there.
What I need from you is the complete module for the counter itself, the segment-decoder logic, a concise test-bench that proves the 0-to-7 sequence, and a Vivado project or clear instructions that allow me to generate the bitstream and dump it straight to the board. Timing must be synchronous to the on-board clock, and resets should be active-low so I can link them to a push-button.
Acceptance criteria
• Functional simulation shows the binary sequence 000–111 rolling over continuously.
• Seven-segment output matches each count value on real hardware.
• Implementation meets timing in Vivado with no critical warnings.
• All source, constraint and script files are delivered so I can rebuild the project end-to-end.
What I need from you is the complete module for the counter itself, the segment-decoder logic, a concise test-bench that proves the 0-to-7 sequence, and a Vivado project or clear instructions that allow me to generate the bitstream and dump it straight to the board. Timing must be synchronous to the on-board clock, and resets should be active-low so I can link them to a push-button.
Acceptance criteria
• Functional simulation shows the binary sequence 000–111 rolling over continuously.
• Seven-segment output matches each count value on real hardware.
• Implementation meets timing in Vivado with no critical warnings.
• All source, constraint and script files are delivered so I can rebuild the project end-to-end.