FPGA using LabsLand

Design a counter that produces an output every clock cycle. The output sequence that
each student downloads from Moodle contains 15 Binary Coded Decimal (BCD) digits
that are unique to each student. Let’s call these output values V0, V1, V2, .. V14. The
count sequence wraps around from V14 back to V0. Here is the normal count sequence:
V0 V1 V2 V3 V4 V5 …V14 V0 V1 V2 V3 V4 V5

There are additional inputs with these properties:
1. iSkip – when asserted the next output skips 4 values (eg from V0 to V5).
2. iRev - when asserted the next output is 2 previous values earlier in the sequence
(eg goes from V5 to V3 ).
3. When both iSkip and iRev are 1, the counter skips 8 values (eg goes from V0 to
V9).
4. When neither iSkip nor iReverse are 1, the counter follows the normal sequence.
5. iRst – when 1 the next output value is V0.
6. iClk - Outputs are produced shortly after each rising iClk edge.
Design your counter using two modules. Module CounterSkipReverse implements the
state sequence of the counter in sequential logic. The module StateToCountSequence
is a combinational logic circuit that maps the state to your BCD V output.

Since your
2 unique BCD V sequence necessarily contains repeated digits (there are 15 in the
sequence) the BCD output cannot act as the state of the counter, as often occurs with
conventional counters. The design challenge here is to work out what state
representation is appropriate. Ensure your design is synthesised by compiling with
Quartus.
Implement your design with a minimum number of flip-flops using Verilog compiled
with Quartus with the standard project settings for a DE2 board. See the assignment
FAQ on Moodle for Quartus settings that are required to ensure a minimum number of
flip-flops are compiled when an FSM is detected in your code by Quartus.
Question 1
Download from Moodle your Verilog template file named assignID.v that defines your
count sequence V0 V1 V2 V3 V4 V5 …V14 . Note that ID in assignID.v is your 8 digit
ID number. This particular file must be used for your Verilog code to solve the above
counter problem. Complete the modules CounterSkipReverse, StateToCountSequence
and CompleteCounter. The file assignID.v must not be shared with, or shown to anyone
else. Do not delete lines in this file since this may invalidate your answer during a
preliminary automatic compilation, marking, plagiarism and collusion checking phase.
Manual marking and checking will be also used after this.
Question 2
In your assignID.v file complete the testbench module AssignmentTestBench that
enables ModelSim to check the correct functionality of your HDL design. Ensure that
you test every transition from every valid state of your circuit. Since we have a reset
action, we are not interested in the property of “self-starting” in this assignment.
Include up to four screen captures from ModelSim showing the testbench simulation
with inputs, outputs and state of your design. Use appropriate display options to
maximise readability. You must also implement your design on the FPGA using Labs

Question 3
Minimise the number of Logic Cells that your design requires after a synthesis
compilation in Quartus with DE2 board settings. This will involve exploring different
implementation strategies, checking them with your testbench and synthesising them in
Quartus. Include a screen capture of Quartus . Here is an example of how to show the registers in a Quartus project
Question 4 Perform a small research and explain how this design may be implemented, adapted, or applied into the real-world scenario. You must include references or citations to justify your explanations. The
more references are included that are relevant, the stronger your explanation and justification will be.

Submit 6 or fewer files:
• assignID.v (Submit ONLY your minimised Logic Cell version from Q3).
• Q2_IDa.jpg , Q2_IDb.jpg, Q2_IDc.jpg , Q2_IDd.jpg
• Q3_ID.jpg
You may submit .png image filesor .jpg files