VHDL Verification Engineer -- 2
Budget: €18 – €36 EUR
Campera Electronic Systems is planning to introduce a Verification methodology in the company verification flow for VHDL designs.
Previous experience on one of the "standard" VHDL verification methodologies (UVVM, OSVVM) or framework (Vunit) is requied.
Previous experience on one of the "standard" VHDL verification methodologies (UVVM, OSVVM) or framework (Vunit) is requied.