RVLDG Paper Replication and Optimization
Budget: ₹600 – ₹1,500 INR
Replicate the reference RVLDG paper exactly in Cadence Virtuoso using 90nm CMOS technology and then develop a novel optimized version with minimum Power Delay Product (PDP).
The final work must be suitable for IEEE conference publication and include all required technical content, figures, tables, simulations, and explanations.
Phase 1: Reference Paper Replication
Implement:
1. Conventional Domino OR Gate (CD-OR)
2. Reduced Delay Domino OR Gate (RD-D-OR)
3. RVLDG (Reference Design)
Technology:
• 90nm CMOS
• Cadence Virtuoso
• Spectre Simulator
• VDD = 1V
Provide:
• Schematic diagrams
• Testbench circuits
• Transistor sizing details
• Input pulse setup
• Output waveforms
• Power calculation
• Delay calculation
• PDP calculation
Phase 2: Novel Optimized Design
Develop a new optimized domino gate architecture based on RVLDG.
Possible Novel Features:
• Adaptive Keeper Control
• Split Bulk-Driven Keeper
• Leakage-Aware Footer Network
• Weak PMOS Level Restorer
• Conditional Evaluation Network
The optimized design must have lower PDP than the all existing previous Design of domino OR ...
• CD-OR
• RD-D-OR
• RVLDG
Required Explanations
For every circuit provide:
1. Circuit Description
- Explain each transistor function.
- Explain keeper operation.
- Explain evaluation network.
2. Working Principle
- Precharge phase operation.
- Evaluation phase operation.
- Dynamic node behavior.
3. Mathematical Analysis
- Delay equations.
- Power equations.
- PDP equations.
- Leakage equations.
4. Novelty Explanation
- Research gap in RVLDG.
- Limitations of RVLDG.
- Proposed improvements.
- Expected advantages.
Required Schematics
Provide publication-quality figures:
• CD-OR schematic
• RD-D-OR schematic
• RVLDG schematic
• Proposed schematic
• Testbench schematic
Required Waveforms
Provide:
• Clock waveform
• Input waveform
• Dynamic node waveform
• Output waveform
Mark:
• Precharge phase
• Evaluation phase
• Delay measurement points
Required Performance Analysis
Calculate:
• Average Power
• Dynamic Power
• Static Power
• Propagation Delay
• PDP
• Leakage Current
• Noise Margin
• Area
• Figure of Merit
Required Comparison Tables
Table 1:
Circuit Comparison
Design| Power| Delay| PDP
Table 2:
Noise Margin Comparison
Table 3:
Leakage Power Comparison
Table 4:
Area Comparison
Table 5:
FOM Comparison
PVT Analysis
Perform simulations for:
• TT
• FF
• SS
• FS
• SF
Temperature:
• -50°C
• 27°C
• 100°C
Supply Voltage:
• 0.8V
• 0.9V
• 1.0V
• 1.1V
• 1.2V
Monte Carlo Analysis
Perform:
• 1000+ iterations
• Power variation
• Delay variation
• PDP variation
Publication Figures
Provide:
1. Power comparison graph
2. Delay comparison graph
3. PDP comparison graph
4. Leakage comparison graph
5. Noise margin comparison graph
6. Monte Carlo histogram
7. PVT comparison plots
IEEE Paper Deliverables
1. Abstract
2. Introduction
3. Literature Review
4. Research Gap
5. Proposed Architecture
6. Mathematical Analysis
7. Simulation Setup
8. Results and Discussion
9. Comparison Tables
10. Conclusion
11. Future Scope
12. References
Important Requirement
The optimized design must clearly outperform CD-OR, RD-D-OR, and RVLDG in terms of Power Delay Product (PDP). All claims must be supported by Cadence simulation results, comparison tables, mathematical analysis, and publication-quality figures suitable for IEEE conference submission.
The final work must be suitable for IEEE conference publication and include all required technical content, figures, tables, simulations, and explanations.
Phase 1: Reference Paper Replication
Implement:
1. Conventional Domino OR Gate (CD-OR)
2. Reduced Delay Domino OR Gate (RD-D-OR)
3. RVLDG (Reference Design)
Technology:
• 90nm CMOS
• Cadence Virtuoso
• Spectre Simulator
• VDD = 1V
Provide:
• Schematic diagrams
• Testbench circuits
• Transistor sizing details
• Input pulse setup
• Output waveforms
• Power calculation
• Delay calculation
• PDP calculation
Phase 2: Novel Optimized Design
Develop a new optimized domino gate architecture based on RVLDG.
Possible Novel Features:
• Adaptive Keeper Control
• Split Bulk-Driven Keeper
• Leakage-Aware Footer Network
• Weak PMOS Level Restorer
• Conditional Evaluation Network
The optimized design must have lower PDP than the all existing previous Design of domino OR ...
• CD-OR
• RD-D-OR
• RVLDG
Required Explanations
For every circuit provide:
1. Circuit Description
- Explain each transistor function.
- Explain keeper operation.
- Explain evaluation network.
2. Working Principle
- Precharge phase operation.
- Evaluation phase operation.
- Dynamic node behavior.
3. Mathematical Analysis
- Delay equations.
- Power equations.
- PDP equations.
- Leakage equations.
4. Novelty Explanation
- Research gap in RVLDG.
- Limitations of RVLDG.
- Proposed improvements.
- Expected advantages.
Required Schematics
Provide publication-quality figures:
• CD-OR schematic
• RD-D-OR schematic
• RVLDG schematic
• Proposed schematic
• Testbench schematic
Required Waveforms
Provide:
• Clock waveform
• Input waveform
• Dynamic node waveform
• Output waveform
Mark:
• Precharge phase
• Evaluation phase
• Delay measurement points
Required Performance Analysis
Calculate:
• Average Power
• Dynamic Power
• Static Power
• Propagation Delay
• PDP
• Leakage Current
• Noise Margin
• Area
• Figure of Merit
Required Comparison Tables
Table 1:
Circuit Comparison
Design| Power| Delay| PDP
Table 2:
Noise Margin Comparison
Table 3:
Leakage Power Comparison
Table 4:
Area Comparison
Table 5:
FOM Comparison
PVT Analysis
Perform simulations for:
• TT
• FF
• SS
• FS
• SF
Temperature:
• -50°C
• 27°C
• 100°C
Supply Voltage:
• 0.8V
• 0.9V
• 1.0V
• 1.1V
• 1.2V
Monte Carlo Analysis
Perform:
• 1000+ iterations
• Power variation
• Delay variation
• PDP variation
Publication Figures
Provide:
1. Power comparison graph
2. Delay comparison graph
3. PDP comparison graph
4. Leakage comparison graph
5. Noise margin comparison graph
6. Monte Carlo histogram
7. PVT comparison plots
IEEE Paper Deliverables
1. Abstract
2. Introduction
3. Literature Review
4. Research Gap
5. Proposed Architecture
6. Mathematical Analysis
7. Simulation Setup
8. Results and Discussion
9. Comparison Tables
10. Conclusion
11. Future Scope
12. References
Important Requirement
The optimized design must clearly outperform CD-OR, RD-D-OR, and RVLDG in terms of Power Delay Product (PDP). All claims must be supported by Cadence simulation results, comparison tables, mathematical analysis, and publication-quality figures suitable for IEEE conference submission.