Digital VLSI / ASIC Project – Verilog, Synthesis, Gate-Level Simulation & Power Analysis (Cadence) -- 2
Budget: $30 – $250 USD
I’m looking for an experienced Digital VLSI / ASIC engineer to complete a small end-to-end RTL-to-power analysis project using Cadence tools.
The project follows a standard ASIC front-end flow: RTL design → synthesis → gate-level simulation → power estimation.
All project structure, templates, and documentation are provided.
The project follows a standard ASIC front-end flow: RTL design → synthesis → gate-level simulation → power estimation.
All project structure, templates, and documentation are provided.
Related categories:
Engineering
Electronics
Verilog / VHDL
Electrical Engineering
Very-large-scale integration (VLSI)