Wearable Medical Device | Electronics System Architect
Budget: €36 – €0 EUR
I am outlining a new, ultra-low-power wearable that centres on health monitoring. The core features I must enable are continuous heart-rate, blood-oxygen (SpO₂) and bio-impedance measurement, all running from a small battery with true all-day wear-time.
What I need from you is a complete system-level architecture—component selection, power-management strategy and clear paths for firmware integration—so that my in-house team can move straight into detailed design and layout. A background in BLE-enabled wearables and experience with sensor AFEs (Maxim, TI, Analog Devices, or similar) will be essential, as will familiarity with Altium (or comparable ECAD), SPICE-based power modelling and low-noise mixed-signal design.
Deliverables
• Architecture document mapping the signal chain from sensor front-end to MCU/BLE SoC, including suggested part numbers
• Power budget spreadsheet showing expected current draw in all operating states and estimated battery life
• High-level schematic block diagram (PDF or Altium) with pin-level notes for critical interfaces
• Draft BOM for key ICs and passives, annotated with availability and cost tiers
• Brief firmware hook plan indicating register sets, sampling rates and interrupt handling required for each metric
Acceptance will be based on the clarity of the documentation, feasibility of the power budget (targeting sub-100 µA average), and alignment of suggested parts with current market availability. If you can add insight on optional fitness or notification features without compromising power, I’m open to hearing it, but the health metrics above are the key drivers.
What I need from you is a complete system-level architecture—component selection, power-management strategy and clear paths for firmware integration—so that my in-house team can move straight into detailed design and layout. A background in BLE-enabled wearables and experience with sensor AFEs (Maxim, TI, Analog Devices, or similar) will be essential, as will familiarity with Altium (or comparable ECAD), SPICE-based power modelling and low-noise mixed-signal design.
Deliverables
• Architecture document mapping the signal chain from sensor front-end to MCU/BLE SoC, including suggested part numbers
• Power budget spreadsheet showing expected current draw in all operating states and estimated battery life
• High-level schematic block diagram (PDF or Altium) with pin-level notes for critical interfaces
• Draft BOM for key ICs and passives, annotated with availability and cost tiers
• Brief firmware hook plan indicating register sets, sampling rates and interrupt handling required for each metric
Acceptance will be based on the clarity of the documentation, feasibility of the power budget (targeting sub-100 µA average), and alignment of suggested parts with current market availability. If you can add insight on optional fitness or notification features without compromising power, I’m open to hearing it, but the health metrics above are the key drivers.