Sat>IP Dongle PCB Design
Budget: $30 – $250 USD
I’m building an ultra-compact dongle that converts satellite TV streams to IP Sat>IP. The core idea is to place a Montage M88RS6060 tuner/demod alongside an Amlogic S905X (1 GB DDR3, 4 GB eMMC) on a miniaturised board that still leaves room for its own power circuitry and a single Gigabit Ethernet jack.
The hint: open to use Open source HW.
Form factor must stay “stick-sized”, so component height, thermal management, and two-layer routing or 4 as you judge discipline are critical. The Ethernet interface must sustain full-duplex gigabit speeds; no other user I/O (USB, HDMI, SD) is required.
If you can hit the same feature set with a cheaper or faster-to-source tuner, demodulator, or SoC, let me know—cost and lead-time are important factors.
Deliverables I expect:
• Schematic capture and complete annotated BOM
• Compact multilayer PCB layout ready for PCBA (Gerber, drill, pick-and-place, assembly drawings)
• Signal-integrity checks around the Ethernet PHY/RGMII and memory buses
• Power tree, thermal estimates, and basic DFM notes
I will validate the design by ordering the first spin exactly from the files you supply, so please ensure footprints, stack-up, and reference design constraints match common Chinese fabs/assemblers. Looking forward to collaborating on a clean, production-ready board.
The hint: open to use Open source HW.
Form factor must stay “stick-sized”, so component height, thermal management, and two-layer routing or 4 as you judge discipline are critical. The Ethernet interface must sustain full-duplex gigabit speeds; no other user I/O (USB, HDMI, SD) is required.
If you can hit the same feature set with a cheaper or faster-to-source tuner, demodulator, or SoC, let me know—cost and lead-time are important factors.
Deliverables I expect:
• Schematic capture and complete annotated BOM
• Compact multilayer PCB layout ready for PCBA (Gerber, drill, pick-and-place, assembly drawings)
• Signal-integrity checks around the Ethernet PHY/RGMII and memory buses
• Power tree, thermal estimates, and basic DFM notes
I will validate the design by ordering the first spin exactly from the files you supply, so please ensure footprints, stack-up, and reference design constraints match common Chinese fabs/assemblers. Looking forward to collaborating on a clean, production-ready board.