Port ESP32 ADS1299 Firmware
Budget: ₹1,500 – ₹12,500 INR
I already have a stable firmware that runs on an ESP32-WROVER-E and drives two daisy-chained ADS1299s for 16 EEG channels. Now the hardware is moving to an ESP32-S3-WROOM-1 and the acquisition board will carry five ADS1299s, giving a total of 24 input channels.
Your job is to take the existing codebase, keep every current feature intact, and extend it so the extra three converters are recognised, initialised and streamed exactly like the original pair. I would like you to stay with the same libraries, framework and tool-chain that the project already uses (ESP-IDF + the TI ADS1299 driver that is in the repo), just refactor where the pin mapping, SPI handling and data structures need to grow.
Key points I will be checking:
• Firmware must compile and flash cleanly on the ESP32-S3-WROOM-1.
• All previous functions (data streaming, Wi-Fi, BLE control commands, on-board filtering) must behave exactly as before.
• The full set of 24 channels appears in the data packets with correct ordering and timing, no dropped samples.
Please provide the updated source, a brief change log, and the sdkconfig you used so I can reproduce the build. If you have access to logic-analyser traces or sample output, attach them; they speed up verification on my rig.
Your job is to take the existing codebase, keep every current feature intact, and extend it so the extra three converters are recognised, initialised and streamed exactly like the original pair. I would like you to stay with the same libraries, framework and tool-chain that the project already uses (ESP-IDF + the TI ADS1299 driver that is in the repo), just refactor where the pin mapping, SPI handling and data structures need to grow.
Key points I will be checking:
• Firmware must compile and flash cleanly on the ESP32-S3-WROOM-1.
• All previous functions (data streaming, Wi-Fi, BLE control commands, on-board filtering) must behave exactly as before.
• The full set of 24 channels appears in the data packets with correct ordering and timing, no dropped samples.
Please provide the updated source, a brief change log, and the sdkconfig you used so I can reproduce the build. If you have access to logic-analyser traces or sample output, attach them; they speed up verification on my rig.