RF Embedded Engineer for Ultrasound Experiments
Budget: $750 – $1,500 USD
We are seeking an experienced RF/Embedded Hardware Engineer to design a custom printed circuit board (PCB) and accompanying firmware to drive a high-power piezoelectric transducer for transcranial focused ultrasound experiments. The system must generate, amplify, and automatically tune a 500 kHz signal into a highly capacitive, low-impedance acoustic load.
The Load (Transducer Specifications)
The system must be designed specifically to drive the following piezoelectric transducer:
Material: SM411
Operating Mode: Thickness mode vibration
Resonant Frequency (fr): 500 kHz ± 10 kHz
Static Capacitance (Cs): 3800 pF ± 20% (measured at 1 kHz, 1 Vrms)
Resonant Impedance (Zm): ≤ 7.6 Ω
Dielectric Loss (Tan∂): 1.5%
Note: At 500 kHz, the capacitive reactance is approximately -83.8 Ω. The matching network must cancel this reactance and transform the amplifier's output impedance down to the 7.6 Ω real load.
System Architecture & Requirements
Digital Control & Signal Generation:
STM32 series MCU capable of high-speed ADC sampling and fast SPI.
Direct Digital Synthesizer (DDS) IC (e.g., AD9959) to generate a precise, sweepable sine wave around the 500 kHz target.
Burst/Pulse envelope control (via VGA like AD8331 or fast RF switching).
Appropriate Low-Pass Filtering (e.g., 2 MHz cutoff) post-DDS.
RF Power Amplification:
Class-D or Class-E amplifier topology utilizing high-speed RF MOSFETs.
High-current RF gate drivers to minimize switching losses.
Target Output: Scalable design capable of 20W to 50W peak burst power.
Adequate thermal management/heatsinking for the switching devices.
Impedance Matching Network:
L-network or π-network utilizing high-power, high-Q components (air-core/ferrite power inductors and high-voltage RF capacitors like Mica/C0G) to withstand high circulating currents.
Feedback & Automatic Resonance Tracking:
Directional coupler and/or V/I sensing transformers on the output stage.
RF phase/gain detector IC (e.g., AD8302) to measure the phase angle between Voltage and Current.
The MCU must read this phase data and continuously adjust the DDS frequency via a control loop to maintain a zero-degree phase shift as the piezo heats up and drifts.
PC Interfacing:
USB/UART connection providing a basic command protocol (Set Frequency, Start/Stop Burst, Set PRF) and telemetry readout (Power, Frequency, Phase Error).
Required Deliverables
Schematic Capture: Complete source files (Altium or KiCad preferred) and PDF.
PCB Layout: Source files, Gerbers, NC Drill files, assembly drawings. Must adhere to RF layout best practices.
Bill of Materials (BOM): Complete list with exact manufacturer part numbers.
Firmware: Well-commented C/C++ source code for the STM32, including the phase-tracking loop and PC protocol.
Design Brief: A short write-up explaining the matching network calculations.
Ideal Candidate
Proven experience in RF Power Amplifier design (Class-D/E in the kHz/MHz range).
Experience designing Impedance Matching Networks for highly reactive loads.
Strong embedded C programming skills for closed-loop control systems.
TO APPLY (Please read carefully):
In the first line of your proposal, please answer the following screening question:
What is your experience with matching highly capacitive loads (like a 3800pF piezo) at RF frequencies, and how would you approach the impedance matching for this specific project? Proposals that do not answer this question will be automatically declined.
The Load (Transducer Specifications)
The system must be designed specifically to drive the following piezoelectric transducer:
Material: SM411
Operating Mode: Thickness mode vibration
Resonant Frequency (fr): 500 kHz ± 10 kHz
Static Capacitance (Cs): 3800 pF ± 20% (measured at 1 kHz, 1 Vrms)
Resonant Impedance (Zm): ≤ 7.6 Ω
Dielectric Loss (Tan∂): 1.5%
Note: At 500 kHz, the capacitive reactance is approximately -83.8 Ω. The matching network must cancel this reactance and transform the amplifier's output impedance down to the 7.6 Ω real load.
System Architecture & Requirements
Digital Control & Signal Generation:
STM32 series MCU capable of high-speed ADC sampling and fast SPI.
Direct Digital Synthesizer (DDS) IC (e.g., AD9959) to generate a precise, sweepable sine wave around the 500 kHz target.
Burst/Pulse envelope control (via VGA like AD8331 or fast RF switching).
Appropriate Low-Pass Filtering (e.g., 2 MHz cutoff) post-DDS.
RF Power Amplification:
Class-D or Class-E amplifier topology utilizing high-speed RF MOSFETs.
High-current RF gate drivers to minimize switching losses.
Target Output: Scalable design capable of 20W to 50W peak burst power.
Adequate thermal management/heatsinking for the switching devices.
Impedance Matching Network:
L-network or π-network utilizing high-power, high-Q components (air-core/ferrite power inductors and high-voltage RF capacitors like Mica/C0G) to withstand high circulating currents.
Feedback & Automatic Resonance Tracking:
Directional coupler and/or V/I sensing transformers on the output stage.
RF phase/gain detector IC (e.g., AD8302) to measure the phase angle between Voltage and Current.
The MCU must read this phase data and continuously adjust the DDS frequency via a control loop to maintain a zero-degree phase shift as the piezo heats up and drifts.
PC Interfacing:
USB/UART connection providing a basic command protocol (Set Frequency, Start/Stop Burst, Set PRF) and telemetry readout (Power, Frequency, Phase Error).
Required Deliverables
Schematic Capture: Complete source files (Altium or KiCad preferred) and PDF.
PCB Layout: Source files, Gerbers, NC Drill files, assembly drawings. Must adhere to RF layout best practices.
Bill of Materials (BOM): Complete list with exact manufacturer part numbers.
Firmware: Well-commented C/C++ source code for the STM32, including the phase-tracking loop and PC protocol.
Design Brief: A short write-up explaining the matching network calculations.
Ideal Candidate
Proven experience in RF Power Amplifier design (Class-D/E in the kHz/MHz range).
Experience designing Impedance Matching Networks for highly reactive loads.
Strong embedded C programming skills for closed-loop control systems.
TO APPLY (Please read carefully):
In the first line of your proposal, please answer the following screening question:
What is your experience with matching highly capacitive loads (like a 3800pF piezo) at RF frequencies, and how would you approach the impedance matching for this specific project? Proposals that do not answer this question will be automatically declined.