ESP32-P4 Display Configuration and Debugging

Job Title
ESP32-P4 (ESP-IDF) – Bring up 720×720 MIPI-DSI In-Cell LCD (JD9365TN) + deliver working demo

Project Overview
I need an experienced embedded/display engineer to bring up a 5.0–5.08" square In-Cell MIPI-DSI display with JD9365TN controller at 720×720 on an ESP32-P4, using ESP-IDF. Current code initialises and runs tests but the display remains blank (backlight behaviour may work depending on variant).
The goal is to deliver a reliable, repeatable working driver + example that I can build and extend (eventually for LVGL).

Hardware / Software Environment
• MCU: ESP32-P4 (https://www.waveshare.com/wiki/ESP32-P4-WIFI6-Touch-LCD-4C)
• Framework: ESP-IDF v5.x (Windows)
• Display: 5.0–5.08" square In-Cell, 720×720, controller JD9365TN, interface MIPI-DSI (https://www.alibaba.com/product-detail/High-Recommend-5-Inch-5-08_1601601194179.html?spm=a2756.trade-list-buyer.0.0.582376e9mXviCX)
• Starting point: Espressif esp_lcd + mipi_dsi example code and a JD9365 panel driver/init table (available in project)

Problem Statement
• The LCD stays blank during test patterns/color bars.
• Need to diagnose/fix likely issues:
o DSI configuration (lane count, lane Mbps, PHY)
o panel timing (pclk, porches, sync), refresh rate stability
o video mode vs command mode configuration
o pixel format (RGB565/666/888) and byte order/packing
o reset/power/backlight sequencing and required delays
o JD9365TN vendor init commands (sleep out/display on/TE, etc.)

Scope of Work (Tasks)
1. Review existing code + reproduce baseline
o validate ESP-IDF project setup and configuration
o validate pin mapping assumptions (reset/backlight/power enables if any)
2. Bring-up + Debug
o confirm DSI bus parameters: lanes, lane Mbps, and mode
o correct 720×720 timing parameters (hsync/vsync/porches) and refresh target
o verify framebuffer → DSI pixel format is correct end-to-end
o ensure JD9365TN is properly exited from sleep/blanking and set to correct mode
o stabilize power-on/reset sequence and required delays
3. Deliver stable rendering demo
o show at least:
 color bars / test pattern
 solid fills / simple shapes (or text)
o verify reliability across repeated power cycles
4. Documentation + Handover
o provide a clear summary of final working parameters and why they were chosen
o provide troubleshooting checklist (what to check if blank screen returns)

Optional (quote separately)
5. Minimal LVGL demo on top of the working panel driver.

Deliverables
• Full updated source files (not snippets):
o updated test_esp_lcd_jd9365*.c (or equivalent bring-up app)
o any required updates to JD9365TN init tables / panel vendor config
o any required Kconfig/CMake changes so it builds cleanly
• Build and flash instructions (exact commands)
• Configuration summary including:
o resolution: 720×720
o lane count + lane Mbps
o pixel clock + porch/sync values
o pixel format
o reset/backlight/power sequencing with delays

Acceptance Criteria
• On boot, LCD consistently displays:
1. color bars/test pattern, and
2. at least one additional render (solid fills, text, or moving pattern).
• Works reliably over 10 consecutive reboots/power cycles.
• Code is maintainable, commented, and parameters are explained.

Required Skills
• Proven experience with MIPI-DSI display bring-up
• Strong C and ESP-IDF experience (esp_lcd, esp_lcd_mipi_dsi)
• Comfortable working from panel datasheets/init sequences and iterating timings

What I Will Provide
• Current ESP-IDF project/repo (includes existing JD9365TN driver/init attempt)
• Serial logs of current behaviour
• Panel documentation/init sequences I have
• Photos/pin mapping as needed

Ownership / IP: All deliverables become my property upon payment.


Please include in your bid: your experience bringing up MIPI-DSI panels (ESP32 or other MCUs), and how you validate lane rate/timing/pixel format during first light.