Confidential Microchip Design & Programming
Budget: $10 – $2,147,483,647 USD
PLEASE READ ENTIRE MESSAGE PRIOR TO BIDDING.
Before I share the technical brief, you will need to sign a standard mutual-NDA; the end product is destined for a new consumer device and I must keep the details under wraps until we are formally covered.
Knowlege of biometrics and gps and LIDaR
Once the paperwork is in place, I will provide a full specification covering both the silicon layout and the embedded firmware. I am looking for a partner who can take the concept from architecture through to a verified, production-ready design, then write and test the on-chip software that drives it.
Core requirement
• Integrate robust wireless communication directly on the die so the finished part can exchange data without an external radio module. Power efficiency and secure pairing are critical, but the exact protocol stack can be discussed once the NDA is signed.
Preferred flow
After agreement on the high-level requirements, I would like to see:
1. Block-level architecture and interface definition
2. RTL / schematic capture with simulation results
3. Firmware (C/assembly) that exercises every peripheral and the radio path
4. Bench or FPGA prototype proving wireless throughput and latency targets
5. Final tape-out package and a concise test plan for production
If you have experience taping out small-to-medium ASICs or advanced FPGAs that later migrated to silicon, plus a track record of writing clean, maintainable embedded code, I would love to review your past work, toolchain preferences (Cadence, Synopsys, Mentor, etc.), and typical turnaround times.
Let me know when you are ready to sign the NDA so we can dive into the specifics.
PLEASE SEND DETAILS OF PRIOR WORk, sene SEALED BIDS
Before I share the technical brief, you will need to sign a standard mutual-NDA; the end product is destined for a new consumer device and I must keep the details under wraps until we are formally covered.
Knowlege of biometrics and gps and LIDaR
Once the paperwork is in place, I will provide a full specification covering both the silicon layout and the embedded firmware. I am looking for a partner who can take the concept from architecture through to a verified, production-ready design, then write and test the on-chip software that drives it.
Core requirement
• Integrate robust wireless communication directly on the die so the finished part can exchange data without an external radio module. Power efficiency and secure pairing are critical, but the exact protocol stack can be discussed once the NDA is signed.
Preferred flow
After agreement on the high-level requirements, I would like to see:
1. Block-level architecture and interface definition
2. RTL / schematic capture with simulation results
3. Firmware (C/assembly) that exercises every peripheral and the radio path
4. Bench or FPGA prototype proving wireless throughput and latency targets
5. Final tape-out package and a concise test plan for production
If you have experience taping out small-to-medium ASICs or advanced FPGAs that later migrated to silicon, plus a track record of writing clean, maintainable embedded code, I would love to review your past work, toolchain preferences (Cadence, Synopsys, Mentor, etc.), and typical turnaround times.
Let me know when you are ready to sign the NDA so we can dive into the specifics.
PLEASE SEND DETAILS OF PRIOR WORk, sene SEALED BIDS