Compact Reusable Camera Engine Development
Budget: $3,000 – $5,000 USD
We are developing a compact, reusable camera engine (the CVE) for use across multiple applications. The CVE is a two-board stacked module that interfaces with a customer-furnished 640×512 focal plane array (FPA) and outputs processed 14-bit video via a standardized 70-pin connector.
A two-board stacked module (≤26×26×12 mm) consisting of:
Board 1 — Sensor Interface (passive)
A passive PCB that accepts the customer-furnished FPA in a 32-pin LCC ceramic socket and routes all signals and power rails to a 30-pin board-to-board stacking connector (Hirose DF40, 2.0 mm stack height). No active components. Includes sensor-specific filter capacitors, an SD0 pull-up resistor, and a DTEMP analog passthrough with series protection resistor.
Board 2 — Engine Board
The active processing board. Must include:
• Processing core (see Section 4 — architecture TBD by contractor at M1)
• Four power regulators: 11 V boost (VDET), 3.3 V low-noise LDO (AVDD), 3.3 V standard LDO (DVDDH), 1.8 V LDO (DVDD), plus power sequencer
• UART header (always populated) — primary control interface
• 70-pin Hirose DF40 (bottom-mount) — platform output interface
• Debug provisions (DNP in production): USB-C, USB FS bridge IC, rail monitor ADC, 3× status LEDs
A two-board stacked module (≤26×26×12 mm) consisting of:
Board 1 — Sensor Interface (passive)
A passive PCB that accepts the customer-furnished FPA in a 32-pin LCC ceramic socket and routes all signals and power rails to a 30-pin board-to-board stacking connector (Hirose DF40, 2.0 mm stack height). No active components. Includes sensor-specific filter capacitors, an SD0 pull-up resistor, and a DTEMP analog passthrough with series protection resistor.
Board 2 — Engine Board
The active processing board. Must include:
• Processing core (see Section 4 — architecture TBD by contractor at M1)
• Four power regulators: 11 V boost (VDET), 3.3 V low-noise LDO (AVDD), 3.3 V standard LDO (DVDDH), 1.8 V LDO (DVDD), plus power sequencer
• UART header (always populated) — primary control interface
• 70-pin Hirose DF40 (bottom-mount) — platform output interface
• Debug provisions (DNP in production): USB-C, USB FS bridge IC, rail monitor ADC, 3× status LEDs