Boundary Scan Debug for SoC Boards

I need an engineer who can set up and execute a boundary-scan (JTAG) workflow aimed at debugging an SoC-based embedded platform. This is to repair a board. The goal is to set up an environment to be able to identify what is the malfunctioning component to replace it and have the board back working. I can provide a good working board to compare.

Environment
• Target hardware: custom SoC board with high-speed memory and mixed-signal peripherals
• Toolchain I already own: Segger J-Link but can adapt to your proposal hard/soft
• Access: remote session to the lab PC,

What I expect you to deliver
1. A working boundary-scan test system and the info that allows me to run tests to identify each component in the board, compare with a good working board and identify damaged IC.
2. Teach me how to set up and use the system.

Let me know what toolchain you propose and what othe info or questions you might have.