Phase 1: Feasibility study - porting Micropython to RISC V SoC running on Arty A7 35T FPGA board with support for makecode editor.

Hi,
I need some help with an initial detailed feasibility study on how to Port Micropython onto an open-source RISC V SoC ( i will send you the exact CPU implementation at a later stage) running on Arty A7 35T FPGA board and how much work is involved with a detailed task list and an estimated timescale.
The projects end goal is to build RISC V porting with all the GPIO & peripherals working in Micropython and the implementation should be compatible with Micropython makecode editor( https://makecode.microbit.org/#editor).
The final objective of this project is to create an open-source Micropython RISC V board with all the required IO functions and support for the makecode editor using USB port.

A similar RISC V Micropython porting like in these repos creaeted by Miodrag Milanović in GitHub.

https://github.com/mmicko/micropython/tree/experimental/ports/freedom-e
https://github.com/mmicko/micropython/tree/legacy/ports/picorv32
https://github.com/mmicko/micropython/tree/legacy/ports/lofive

Some additional info:

https://forum.micropython.org/viewtopic.php?t=1049

Regards,

Prathap