I need VHDL Designer
Budget: ₹1,500 – ₹12,500 INR
This is a final year project. We are struck with simulation. Need to debug our program, or else develop the project from scratch.
I am attaching the code that we have wrote for your reference.
We used Quartus altera for coding, and model sim for simulation. The development board is a cyclone 2.
There were no errors as such. The code would simulate and after one clock cycle, the output would become 'Z'.
From what I understood, the main issue is the interconnection between all the modules.
I am attaching the code that we have wrote for your reference.
We used Quartus altera for coding, and model sim for simulation. The development board is a cyclone 2.
There were no errors as such. The code would simulate and after one clock cycle, the output would become 'Z'.
From what I understood, the main issue is the interconnection between all the modules.