design of TSPC DFF in Cadence

using any ieee paper on the TSPC DFF, implement the circuits from the schematic to the layout,design
specifcations should be the performance described in the published paper.

ˆ Schematic simulation - Cadence Virtuoso
ˆ Layout - Cadence Layout tool
ˆ DRC and LVS
ˆ Post-layout simulation

sample paper is attached