Verilog and Vivado Tutor -- 2

I am currently working on a project to combine a custom kernel with an AI accelerator (DPU) from Xilinx. Currently I am facing some issues with integration and bitstream generation. If you have some experience linking xo files and working with Vivado and/or Vitis I would love to pick your brain. This is mostly a consulting and tutor gig. Please mention some experience in your bid.