Verilog Code for 1-Wire Secure EEPROM Interface with Zynq Zed Board

I am looking for an experienced FPGA developer to write functional Verilog code for interfacing a 1-wire secure EEPROM with a Zynq Zed Board. The EEPROM includes SHA-1 authentication. The deliverables should include:
- Fully functional Verilog code for the interface.
- Proper handling of SHA-1 authentication.
- Compatibility with the Zynq Zed Board.