RISC-V Instruction Set & CPU Extension Project
Budget: $30 – $60 CAD
This project focuses on exploring the RISC-V architecture, with emphasis on instruction set decoding, enhancing a single-cycle processor, and analyzing a 5-stage pipeline.
The ideal candidate will have a solid background in computer architecture, particularly with hands-on experience in RISC-V.
Key Responsibilities:
Decode and implement instructions from the RISC-V instruction set.
Extend a single-cycle CPU to support new operations.
Analyze and design a 5-stage pipeline with forwarding and hazard handling.
Skills and Experience Required:
Strong knowledge of RISC-V architecture.
Experience in CPU datapath design and control signal logic.
Ability to identify and resolve pipeline hazards effectively
The ideal candidate will have a solid background in computer architecture, particularly with hands-on experience in RISC-V.
Key Responsibilities:
Decode and implement instructions from the RISC-V instruction set.
Extend a single-cycle CPU to support new operations.
Analyze and design a 5-stage pipeline with forwarding and hazard handling.
Skills and Experience Required:
Strong knowledge of RISC-V architecture.
Experience in CPU datapath design and control signal logic.
Ability to identify and resolve pipeline hazards effectively