PCB Design for Particle.IO carrier board
Budget: $30 – $250 USD
1) Purpose & Scope
Compact carrier board with 3 switched 12 V outputs, 2 LAN ports, Particle Boron for cellular/cloud, ESP32 for Ethernet + debug Wi-Fi. Supports watchdog, current telemetry, and remote control.
2) High-Level Architecture
Power input and protection, regulators, 3 high-side switched outputs, Ethernet switch (KSZ8863), Particle Boron, ESP32-WROOM-32E with PCB antenna, RJ45 MagJacks, WAGO connectors.
3) Key Parts
• - Particle Boron sockets: PPTC161LFBN-RC, 6-534237-0
• - ESP32-WROOM-32E (PCB antenna)
• - KSZ8863RLL 3-port switch
• - TPS2H160B-Q1 dual high-side switch (OUT_A, OUT_B)
• - TPS1H200A-Q1 single high-side switch (OUT_C)
• - LMR33630 (12V->3V3)
• - LMR33620 (12V->5V)
• - WAGO 2601-1102 for IN/OUT connectors
• - SMBJ24A TVS, SS34 Schottky, Bourns MF-MSMF200 PPTC fuse
• - RJ45 MagJacks (Bel/HALO)
• - 0805 passives preferred; 1206 for bulk caps
4) Interfaces & Nets
• - Power: +12V_IN → F1 → D3 → +12V bus → regulators & switches
• - Outputs: OUT_A (J13), OUT_B (J14), OUT_C (J15), ≥1.5 A each, default ON
• - Current sense: IS pins → RC → ESP32 ADC1 (GPIO36/39/33)
• - FAULT pins → ESP32 GPIOs
• - ESP32↔KSZ: RMII, 50 MHz clock, MDC/MDIO
• - ESP32↔Boron: UART (3.3 V)
• - Wi-Fi: debug-only, PCB antenna at edge, keep-out enforced
5) Electrical Requirements
• - Input: 10.8–14.4 V (design for 9–16 V with TVS)
• - Outputs: ≥1.5 A each continuous
• - Protections: reverse polarity, surge/ESD, hi-side OC/OT
• - Failsafe: all outputs ON at power-up
6) PCB Requirements
• - 4 layers: L1 signals, L2 solid GND, L3 power planes, L4 signals
• - Impedance: 100 Ω diff (Ethernet), 50 Ω SE (RMII/clock)
• - Placement: RJ45 top edge, WAGO right edge, Boron center (sockets, under-board passives), ESP32 bottom edge (antenna clearance), power input left side
• - Thermal vias for regulators and switches
• - Keep-out under ESP32 antenna and Boron antenna
7) Test, Debug & Jumpers
• - Test pads: +12V, +5V_BORON, BORON_VIN, +3V3, +3V3_A, GND, UART, EN/FAULT/IS nets
• - 0 Ω jumpers (0805): RJP1, RJP2, RJP3, RJP4 for isolation and current probing
• - Optional bleeder resistors on outputs (DNP)
8) Deliverables
• - schematic (blocks: power, hi-side switches, ESP32, Boron, KSZ8863+RJ45)
• - Net labels as defined above
• - ERC/DRC clean, impedance notes
• - 4-layer PCB layout with placement guidance
• - BOM with MPNs, pick-place, 3D model export
• - Bring-up checklist: power rails, UART, switch straps, output switching
Compact carrier board with 3 switched 12 V outputs, 2 LAN ports, Particle Boron for cellular/cloud, ESP32 for Ethernet + debug Wi-Fi. Supports watchdog, current telemetry, and remote control.
2) High-Level Architecture
Power input and protection, regulators, 3 high-side switched outputs, Ethernet switch (KSZ8863), Particle Boron, ESP32-WROOM-32E with PCB antenna, RJ45 MagJacks, WAGO connectors.
3) Key Parts
• - Particle Boron sockets: PPTC161LFBN-RC, 6-534237-0
• - ESP32-WROOM-32E (PCB antenna)
• - KSZ8863RLL 3-port switch
• - TPS2H160B-Q1 dual high-side switch (OUT_A, OUT_B)
• - TPS1H200A-Q1 single high-side switch (OUT_C)
• - LMR33630 (12V->3V3)
• - LMR33620 (12V->5V)
• - WAGO 2601-1102 for IN/OUT connectors
• - SMBJ24A TVS, SS34 Schottky, Bourns MF-MSMF200 PPTC fuse
• - RJ45 MagJacks (Bel/HALO)
• - 0805 passives preferred; 1206 for bulk caps
4) Interfaces & Nets
• - Power: +12V_IN → F1 → D3 → +12V bus → regulators & switches
• - Outputs: OUT_A (J13), OUT_B (J14), OUT_C (J15), ≥1.5 A each, default ON
• - Current sense: IS pins → RC → ESP32 ADC1 (GPIO36/39/33)
• - FAULT pins → ESP32 GPIOs
• - ESP32↔KSZ: RMII, 50 MHz clock, MDC/MDIO
• - ESP32↔Boron: UART (3.3 V)
• - Wi-Fi: debug-only, PCB antenna at edge, keep-out enforced
5) Electrical Requirements
• - Input: 10.8–14.4 V (design for 9–16 V with TVS)
• - Outputs: ≥1.5 A each continuous
• - Protections: reverse polarity, surge/ESD, hi-side OC/OT
• - Failsafe: all outputs ON at power-up
6) PCB Requirements
• - 4 layers: L1 signals, L2 solid GND, L3 power planes, L4 signals
• - Impedance: 100 Ω diff (Ethernet), 50 Ω SE (RMII/clock)
• - Placement: RJ45 top edge, WAGO right edge, Boron center (sockets, under-board passives), ESP32 bottom edge (antenna clearance), power input left side
• - Thermal vias for regulators and switches
• - Keep-out under ESP32 antenna and Boron antenna
7) Test, Debug & Jumpers
• - Test pads: +12V, +5V_BORON, BORON_VIN, +3V3, +3V3_A, GND, UART, EN/FAULT/IS nets
• - 0 Ω jumpers (0805): RJP1, RJP2, RJP3, RJP4 for isolation and current probing
• - Optional bleeder resistors on outputs (DNP)
8) Deliverables
• - schematic (blocks: power, hi-side switches, ESP32, Boron, KSZ8863+RJ45)
• - Net labels as defined above
• - ERC/DRC clean, impedance notes
• - 4-layer PCB layout with placement guidance
• - BOM with MPNs, pick-place, 3D model export
• - Bring-up checklist: power rails, UART, switch straps, output switching