Logic Gates Design for 3-Stage Counter
Budget: £20 – £250 GBP
The block diagram of TABLE 1 shows a 3-stage asynchronous counter that is used to count a series of randomly occurring input pulses.
The Q outputs of the counter are used to drive a logic circuit that gives the output in TABLE 1.
Design the logic circuit to realise the desired ABCD outputs.
Simulate your circuit using the Multisim.com template provided, including an image of all waveforms for at least one full cycle
Please provide an image of all waveforms for at least one full cycle.
You will need to download the 'PROTEUS 8 DEMONSTRATION'
https://www.labcenter.com/free-trial/
https://tuonline.tees.ac.uk/d2l/le/dropbox/12286/2971/DownloadAttachment?fid=427326
The Q outputs of the counter are used to drive a logic circuit that gives the output in TABLE 1.
Design the logic circuit to realise the desired ABCD outputs.
Simulate your circuit using the Multisim.com template provided, including an image of all waveforms for at least one full cycle
Please provide an image of all waveforms for at least one full cycle.
You will need to download the 'PROTEUS 8 DEMONSTRATION'
https://www.labcenter.com/free-trial/
https://tuonline.tees.ac.uk/d2l/le/dropbox/12286/2971/DownloadAttachment?fid=427326