FPGA designer for Artix 7
Budget: $750 – $1,500 USD
Also have questions here that you can answer for now it's optional but will be asked in second round of interviews
FPGA Questions
Device we are trying to work with is XC7A35T-2FGG484I (Artix 7). We do plan on hiring you, we would like for you to answer these questions which will help us gauge how to structure the project.
How familiar are you with microblaze?
Once having microblaze cpu setup, is firmware compile time similar to other mcu roughly in the seconds or does it take longer?
How familiar are you with design-reuse website?
Is it feasible to program FPGA to act like a pass-through meaning say a signal from one side of the FPGA going to the another pin, effectively creating a multiplexor, could this work with high speed signals at the 1gbps level, and the serdes level
I did see mutpliple pins for serdes not just 4 transceiver pairs but more that one 4 pairs is this multiplexed?
Have you ever implemented the PCI functionality of an FPGA directly to MPU?
For IP cores from websites like design-reuse or github is it feasible for production, meaning allowing thousands of users to use? Or may there be some clause for royalty etc.?
Say we run out of resources registers, lut, etc. what is the feasibility of running another RTL in production, meaning storing the RTL info somewhere in memory and dynamically reconfigure the FPGA? Say it's complex, What is the time to do this? How big will the RTL code be? Will this require software or is it possible to have a binary
like mcu and load with some bootloader like mcu?
FPGA Questions
Device we are trying to work with is XC7A35T-2FGG484I (Artix 7). We do plan on hiring you, we would like for you to answer these questions which will help us gauge how to structure the project.
How familiar are you with microblaze?
Once having microblaze cpu setup, is firmware compile time similar to other mcu roughly in the seconds or does it take longer?
How familiar are you with design-reuse website?
Is it feasible to program FPGA to act like a pass-through meaning say a signal from one side of the FPGA going to the another pin, effectively creating a multiplexor, could this work with high speed signals at the 1gbps level, and the serdes level
I did see mutpliple pins for serdes not just 4 transceiver pairs but more that one 4 pairs is this multiplexed?
Have you ever implemented the PCI functionality of an FPGA directly to MPU?
For IP cores from websites like design-reuse or github is it feasible for production, meaning allowing thousands of users to use? Or may there be some clause for royalty etc.?
Say we run out of resources registers, lut, etc. what is the feasibility of running another RTL in production, meaning storing the RTL info somewhere in memory and dynamically reconfigure the FPGA? Say it's complex, What is the time to do this? How big will the RTL code be? Will this require software or is it possible to have a binary
like mcu and load with some bootloader like mcu?