Design a power module for network board + MCU -- 2

# What is the project about:

We are building a cost-optimized, modular Time-Sensitive Networking (TSN) switch based on the Microchip LAN9645xF. We need a Power Electronics Engineer to design the critical "Power Module" that feeds the system.

You will own the power architecture from Input to Silicon, ensuring that a noisy industrial 24V line or a consumer USB-C charger can both be converted into ultra-clean, stable rails (1.15V, 2.5V, 3.3V) without crashing the switch or failing EMI certification.

# Goals
1. Power Stage Design (Dual Input Architecture)
Design a robust "OR-ing" input stage that seamlessly switches between:
- Input A (Industrial): 12V–48V DC via Barrel Jack (must survive 60V transients).
- Input B (Consumer): USB-C (5V @ 3A). Note: No complex PD controller needed, just basic CC-pin pull-downs for 5V/3A negotiation.
Design the DC/DC Buck Stage:
- Step down high voltage (up to 48V) to a stable 5V intermediate bus.
- Select cost-effective, high-efficiency buck converters (e.g., MPS, TI, or Microchip) that fit the <$5 budget for the power section.

2. Low-Voltage Regulation (The LAN9645xF Requirements https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/LAN9645xF-Data-Sheet-DS00006065.pdf )
Generate the specific rails required by the Switch IC and microcontroller with strict sequencing:
- 1.15V (Core): High current (~1A), fast transient response. Must use a switching regulator, not LDO, to manage heat with a power budget of around 5
- 2.5V (Analog/PHY): Ultra-low noise ripple (<30mVpp) for Gigabit signal integrity up to 9 gigabit ethernet port over 100 Meter.
- 3.3V (IO/MCU): Separated between switch I/O and MCU: Clean power for the STM32 module.
- Sequencing: Ensure 3.3V comes up before 1.15V (or per datasheet specifications) to prevent latch-up.
- Be able to sustain power surge and peaks.

3. EMI/EMC Validation & Hardening
Pre-Compliance Design: Design the PCB with 4-layer stack-up best practices (Ground stitching, shielded inductors, minimized switch nodes) to pass CISPR 32 Class B (Residential) and Class A (Industrial).
- Input Protection: Implement protection against:
- Surge/Burst (IEC 61000-4-5): TVS diodes and fuses.
- ESD (IEC 61000-4-2): Handling contact discharge up to ±4kV on connectors.
- Test Plan Creation: Define the validation plan for the prototype, including "Load Step" tests (0% to 100% traffic load) to ensure V_Core (1.15V) never dips below brownout levels.

4. External connector, Board to board solution
The board is meant to be developed as an external module. Therefore, the power board output and/or input signals should be provided using a board to board connector that can handle the whole power.

# Required Skills
- Experience: 2+ years in DC/DC power supply design for embedded systems.
- Silicon Familiarity: Experience powering complex SoCs/FPGAs (Microchip, NXP, Xilinx) requiring multiple voltage rails (Core vs. IO).
- EDA Tools: Proficiency in KiCad (preferred) or Altium Designer.
- EMI Knowledge: In-depth understanding of why power supplies fail Radiated Emissions (loop areas, rising edges) and how to fix it without expensive metal shielding.

# Deliverables
- Simulation Report: SPICE simulation of the 12V→1.1V buck converter showing transient response during a "0 to 100% Traffic Burst."
- Routed board & Schematic & BOM: Complete design of the Power Board (Input Protection + Regulators) fitting the <$10 BOM target ready for production.
- EMI Risk Assessment: A markup of the layout highlighting "Hot Loops" and mitigation strategies (snubbers, beads).

# For now
- Please come back to me to let me know what is the timeline
- Feel free to ask me any specific questions

# Future
- Once this board is done, the MCU board and Network board will be necessary. If you succeed, there is a huge possibility to continue as part of this two other projects.