IC Design Layout on 65 nm Cadence
Budget: $30 – $250 USD
I need a skilled professional with substantial experience in IC design layout specifically focusing on transistor layout using Cadence. The task will involve making the layout of an 8 transistor SRAM. The schematic is already done, only the layout needs to be done. Need to follow the minimum length and width.
This involved using cadence 65nm technology
Ideal Skills:
- Proficient in 65nm Cadence IC design tools
- Extensive experience in transistor layout
- Physical design experience making layout from looking at the schematic
- DRC, LVS needs to pass for the SRAM cell
Please note that this project requires keen attention to detail and a strong understanding of Carence IC design principles,
This involved using cadence 65nm technology
Ideal Skills:
- Proficient in 65nm Cadence IC design tools
- Extensive experience in transistor layout
- Physical design experience making layout from looking at the schematic
- DRC, LVS needs to pass for the SRAM cell
Please note that this project requires keen attention to detail and a strong understanding of Carence IC design principles,