Create a 4-Bit Binary Synchronous Up Counter in Electric VLSI

Job ID: 36414500

Budget: $30 – $250 USD

Design 4-bit Up binary ripple counter that counts from 0000 to 1111. Provide all timing diagrams for every counting from 0000 to 1111 in one increment at a time. Provide all timing delays using LTSPICE simulations for each count. Provide IRSIM to show the proper functions of the 4-Bit counter.

You may find the gate level schematic and timing of the Up counter in the following links. There are many tutorials available on-line including YouTube. You may implement your design using D F/F or JK F/F; however, use the rising edge of the clock to make the timing counts.

Synchronous Counter and the 4-bit Synchronous Counter (electronics-tutorials.ws)
www.electronics-tutorials.ws/counter/count_3.html




This is a hint for LTSPICE: For the parasitic extraction, follow exactly what it says in this link: http://cmosedu.com/cmos1/ltspice/ltspice_electric.htm. In the drop-down menu labeled "Parasitics", select the "Conservative RC" option instead of the default "Trans area/Perim only" option. This is what gives you the R and C values when you click Tools -> Simulation (Spice) -> Write Spice Deck. In the tutorial it tells you to save the file C5_models.txt to C:\Electric for SPICE simulations. Then in the LTSPICE code you have to write ".include C:\Electric\C5_models.txt".


I need the .jileb file!