Cadence Virtuoso Composer task
Budget: $10 – $30 USD
Three inverter configurations need to be analyzed in this lab: the resistive load, the Enhancement modeNFET and the static CMOS schematics, all of which should be drawn using cadence virtuoso composer.
Prepare each inverter in a schematic using the 4-tenninal NFET (nmos4) and PFET (pmos4) devices as
needed. Additional components for the design include the capacitor, the resistor, supply nets and ground
as needed. The DC simulation of the inverters will require a DC voltage supply to be included in the
schematic. A capacitance of0.015pF (l5fF) must be added for each configuration.
Prepare each inverter in a schematic using the 4-tenninal NFET (nmos4) and PFET (pmos4) devices as
needed. Additional components for the design include the capacitor, the resistor, supply nets and ground
as needed. The DC simulation of the inverters will require a DC voltage supply to be included in the
schematic. A capacitance of0.015pF (l5fF) must be added for each configuration.