wearable ultrasoinc sensor
Budget: $15 – $25 USD
Hi,
I hope you are doing great. I am Rouzbeh Molaei from Iran. I am a second-year Ph.D. student at the Department of biomedical engineering at UT Dallas. I am working on the project of "Wearable Ultrasound Sensor". I would basically want to redesign the paper attached here. At the moment, I am debugging the serial LVDS capture code from my Analog-Front_end (AFE5832LP) to FPGA (Zynq Ultrascale_plus MPSoC).
As I mentioned, I want to connect an acquisition board (model AFE5832LP) to the Zynq Ultrascale\+ board (ZCU104) via TI's FMC-ADC connector. The AFE5832LP board consists of 32channels, 16 ADCs with 12 bits resolution, and 40MHz sampling frequency. The data is received by LVDS. I receive two differential pairs for each channel and four differential pairs of the clock, two for the frame clock and two for the bit clock. Data is received in DDR mode. The bit clock is aligned with the center of the data. Well, I have a frame clock frequency of 40MHz, a bit clock of 200MHz, and a data rate of 400Mbps.
I am the only one in our lab working on this project and UTD does not have a digital system design department in which I could find an FPGA engineer to ask my questions. Is there any possibility for you to help me in this regard so I can learn this from you and also pay for your service?
I hope you are doing great. I am Rouzbeh Molaei from Iran. I am a second-year Ph.D. student at the Department of biomedical engineering at UT Dallas. I am working on the project of "Wearable Ultrasound Sensor". I would basically want to redesign the paper attached here. At the moment, I am debugging the serial LVDS capture code from my Analog-Front_end (AFE5832LP) to FPGA (Zynq Ultrascale_plus MPSoC).
As I mentioned, I want to connect an acquisition board (model AFE5832LP) to the Zynq Ultrascale\+ board (ZCU104) via TI's FMC-ADC connector. The AFE5832LP board consists of 32channels, 16 ADCs with 12 bits resolution, and 40MHz sampling frequency. The data is received by LVDS. I receive two differential pairs for each channel and four differential pairs of the clock, two for the frame clock and two for the bit clock. Data is received in DDR mode. The bit clock is aligned with the center of the data. Well, I have a frame clock frequency of 40MHz, a bit clock of 200MHz, and a data rate of 400Mbps.
I am the only one in our lab working on this project and UTD does not have a digital system design department in which I could find an FPGA engineer to ask my questions. Is there any possibility for you to help me in this regard so I can learn this from you and also pay for your service?