8-bit Addressable Latch with built in 1of 8 Decoder
Budget: $10 – $30 USD
Design an 8-bit Addressable Latch with built in 1 of 8 Decoder. The circuit is composed of three stages, the decoder, latch system and a buffer output. The device has four modes of operation. In the addressable latch mode, the signal on DATA IN is written into the addressed latch. The addressed latch follows the data input with all non−addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one−of−eight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state
In the Reset mode, all outputs are LOW and unaffected by the address and data inputs. You can choose one of the following logic families: CMOS, pseudo-NMOS, pass transistor or dynamic. In addition, you must optimize the circuit as to minimize propagation delay. You are free to choose your logic swing. The noise margins should at least be 10% of the voltage swing. Test this by computing the VTC between one of the inputs and the output signals (with the other outputs set to the appropriate values) for a static design. For a dynamic circuit, apply an input signal with a 10% value added to the input and observe the outputs.
In the Reset mode, all outputs are LOW and unaffected by the address and data inputs. You can choose one of the following logic families: CMOS, pseudo-NMOS, pass transistor or dynamic. In addition, you must optimize the circuit as to minimize propagation delay. You are free to choose your logic swing. The noise margins should at least be 10% of the voltage swing. Test this by computing the VTC between one of the inputs and the output signals (with the other outputs set to the appropriate values) for a static design. For a dynamic circuit, apply an input signal with a 10% value added to the input and observe the outputs.