VHDL Project Elevator

I need this by Monday the latest please. Its VHDL and the project idea is attached. Please abide by the following instructions also.

Please submit your written report (narrative) as a separate .pdf file

Please zip up your entire Quartus project folder as a .zip file and submit the .zip file as well. Make sure that this zip file includes all your VHDL source files and the Quartus BDF diagram file (if any). Without those, there'll be no grade for your Quartus project. If those source files are missing in your zip file submission, your submission will not be graded.

The written report should be written as follows:

Make sure to enter names of all members in your project.
Do not write an essay. It's a technical writing, which is expected to be structured with a proper title, sections, subsections, bullet points, diagrams, and so on. Make sure to put introduction and conclusion sections.
Do not include VHDL source code in your written report this time, as your source code should be submitted separately in the zip file.
Explain what your project is, what the input/output specification is, what features you implemented (e.g., for Pong, what extra features you implemented in addition to the basic Pong game playing).
Insert screenshot of your top-level entity's block diagram (from BDF or Quartus netlist viewer) if it's different from that of the VGA lab.
If you have added any finite state machine on your final project implementation (which should be highly likely and expected), insert a state transition diagram.
Explain architecture of your design. Explain each sub-module (entity).
Narrate your reflections on the project, like what issues were most difficult, how you solve them, and so on.