TFET Capacitance Model Development and Simulation on Cogenda Visual TCAD

I'm seeking an expert in numerical simulation and circuit design for Tunneling Field-Effect Transistors (TFETs).

Key Requirements:
- Develop a comprehensive compact model for TFET capacitance that includes parasitic, inversion, and gate-drain capacitances (Cgd).
- This model should be calibrated with Computer-Aided Design (CAD) data to enhance its accuracy.
- Investigate the influence of drain design and gate length on gate–drain capacitance (Cgd).
- Propose and explore strategies to minimize switching delays in TFET-based circuits.

Ideal Skills:
- Profound knowledge and experience in TFETs vs MOSFETs gate capacitance partitioning.
- Proficiency in model development and numerical simulations.
- Familiarity with CAD data and its application in circuit design.
- Innovative thinking for developing solutions to reduce switching delay.

The primary aim of this project is the development of a detailed and precise model for TFET capacitance. I'm looking for a freelancer who can accurately calibrate this model with CAD data, and offer insightful analyses and practical solutions.