QPSK/QAM TRANSCEIVER USING ZEDBOARD
Budget: ₹250,000 – ₹500,000 INR
Dear Sir/Madam
I am Sathish Danthala, Technical Manager, from Communication Division, ECIL, Hyderabad.
• Presently our team is working on design and development of Signal Processing module. As a part of this we have to read audio sample from audio Codec, TOD data from GPS receiver and perform base band digital modulations on this data/audio samples and should convert into a fixed analog IF frequency.
• The architecture should be like SDR architecture, base band I/Q samples will be modulated in to base band modulated I/Q samples. To implement this architecture the following design has been adopted by us.
We have selected "Zedboard” ZYNQ/FPGA for base band signal processing & AD9361 RF Agile transceiver as a RF front end.
For Data Packetization, Data enocding, decoding we are using ZYNQ/ARM processor.
From the available open sources we have designed HDL project in FPGA (VIVADO-2020.2) and Software project in Xilinx Vitis and Modulator IP cores generated from Simulink model based deisign.
We need help in data packetization, data encoding & decoding, channel encoding & decoding, controlling, sending and receiving the data or audio samples from the base band Modulator IP cores generated from MATLAB/SIMULINK model based design.
I am Sathish Danthala, Technical Manager, from Communication Division, ECIL, Hyderabad.
• Presently our team is working on design and development of Signal Processing module. As a part of this we have to read audio sample from audio Codec, TOD data from GPS receiver and perform base band digital modulations on this data/audio samples and should convert into a fixed analog IF frequency.
• The architecture should be like SDR architecture, base band I/Q samples will be modulated in to base band modulated I/Q samples. To implement this architecture the following design has been adopted by us.
We have selected "Zedboard” ZYNQ/FPGA for base band signal processing & AD9361 RF Agile transceiver as a RF front end.
For Data Packetization, Data enocding, decoding we are using ZYNQ/ARM processor.
From the available open sources we have designed HDL project in FPGA (VIVADO-2020.2) and Software project in Xilinx Vitis and Modulator IP cores generated from Simulink model based deisign.
We need help in data packetization, data encoding & decoding, channel encoding & decoding, controlling, sending and receiving the data or audio samples from the base band Modulator IP cores generated from MATLAB/SIMULINK model based design.