Integrated circuit testing
Budget: $10 – $30 USD
Introduce a design for testability method to sequential circuit.
Steps:
1. Implement design for testability full scan or partial scan method to sequential circuit (CUT).
The CUT consists of at least 6 D flip-flops and 10 logic gates.
2. Inject 3 faults only to the circuit.
3. Discuss and analysis each faults in terms of :
a. what is the test pattern needed.
b. show how the fault can be observed at output.
You can get some idea from http://ieeexplore.ieee.org or any research database/reference
books.
Use Quartus tool to design the circuit and simulation (waveform) process.
Report format:
1. Explain how the DFT is implemented on the CUT.
2. Calculate area overhead.
3. Discuss and analysis the simulation (waveform) part.
Steps:
1. Implement design for testability full scan or partial scan method to sequential circuit (CUT).
The CUT consists of at least 6 D flip-flops and 10 logic gates.
2. Inject 3 faults only to the circuit.
3. Discuss and analysis each faults in terms of :
a. what is the test pattern needed.
b. show how the fault can be observed at output.
You can get some idea from http://ieeexplore.ieee.org or any research database/reference
books.
Use Quartus tool to design the circuit and simulation (waveform) process.
Report format:
1. Explain how the DFT is implemented on the CUT.
2. Calculate area overhead.
3. Discuss and analysis the simulation (waveform) part.