FPGA VHDL RTL Simulation

Project: RTL Design and Simulation for FPGA (VHDL)

Goal:
Develop and verify a complete FPGA RTL design in VHDL, including all core modules and corresponding testbenches, to ensure the system behaves as specified before synthesis and hardware bring-up.


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Scope of Work

1. RTL Development

Implement VHDL source modules according to provided system requirements, diagrams, or behavioral specifications.

Establish a clean, hierarchical structure (top-level plus submodules).

Ensure synthesizable and portable code compatible with major FPGA toolchains (Vivado, Quartus, etc.).



2. Testbench and Verification

Develop a self-contained testbench that drives realistic stimulus through each module and the top-level design.

Run simulations in ModelSim, QuestaSim, or GHDL, providing waveform captures and logs.

Annotate any functional issues, corner cases, or unexpected timing behaviors.



3. Documentation & Deliverables

Provide the following deliverables:

VHDL RTL source files

Testbench files

Simulation scripts (Makefile or TCL)

A concise PDF or Markdown report summarizing design structure, simulation results, and recommendations






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Nice-to-Have

Automated regression or coverage reporting

Early guidance on timing or resource usage before synthesis

Clean coding style with comments and inline assertions for future maintenance



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Key Requirements

Expert-level VHDL/FPGA design and simulation skills

Experience building testbenches and running complete verification flows

Strong understanding of timing closure, FSMs, and pipelined architectures

Deliverables must be reproducible, portable, and clearly documented



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Goal for this posting: Find an experienced FPGA engineer who can handle both RTL creation and simulation verification—not just testbench development.