Vivado Chirp Generator & FFT Integration fot Frequency detection
Budget: $30 – $250 USD
I need a complete RTL design in Vivado that produces an up-chirp based on a sinusoidal input and sweeps from 50 MHz up to 55 MHz. Once generated, this signal must feed directly into an 8192-point FFT, so I can observe the dominant frequency bins in hardware.
The core tasks are:
• Write synthesizable VHDL / Verilog for the chirp oscillator, parameterised for the 50–55 MHz sweep.
• Instantiate and configure the Xilinx FFT IP for 8192 points, wire it to the chirp stream, and handle any required data-format conversions or hand-shaking.
• Provide timing-compatible top level, constraints, and a self-checking test-bench that sweeps the chirp, captures the FFT output, flags the peak bins and dominant frequencies.
Acceptance is straightforward: when I run the supplied simulation and then program the FPGA, I should see the chirp transition cleanly across the stated band and the FFT output highlight the correct moving peak without spurs or dropped samples.
More projects to follow for right skilled engineer.
The core tasks are:
• Write synthesizable VHDL / Verilog for the chirp oscillator, parameterised for the 50–55 MHz sweep.
• Instantiate and configure the Xilinx FFT IP for 8192 points, wire it to the chirp stream, and handle any required data-format conversions or hand-shaking.
• Provide timing-compatible top level, constraints, and a self-checking test-bench that sweeps the chirp, captures the FFT output, flags the peak bins and dominant frequencies.
Acceptance is straightforward: when I run the supplied simulation and then program the FPGA, I should see the chirp transition cleanly across the stated band and the FFT output highlight the correct moving peak without spurs or dropped samples.
More projects to follow for right skilled engineer.
Related categories:
Electronics
Verilog / VHDL
Microcontroller
FPGA
Embedded Systems
Digital Signal Processing
Simulation