RMCM FIR Filter Verilog Simulation
Budget: ₹1,500 – ₹12,500 INR
I need a clean, Segmened Analysis and Necessity first search algorithm implementation using python then reduced coefficients constants will be given as input to rmcm block as hardcoded values in Verilog well-structured Verilog implementation of an FIR filter that follows the RMCM (Reconfigurable Multiple Constant Multiplication)architecture. The goal is strictly functional verification, so everything happens inside ModelSim; no FPGA bitstream or ASIC sign-off is required.
The code must be synthesizable, but the only deliverables I need at this stage are:
• Verilog source files that realise the RMCM-based FIR
• A self-checking ModelSim test-bench with a small set of example input vectors and expected outputs
• Simulation snapshots or log files that prove the filter’s impulse response and steady-state behaviour match the theoretical values
If the design is parameterisable (tap count, word-length, coefficient set) that will make later hardware migration easier, but it is optional—clarity and correctness take priority.
Please keep the directory tree simple, comment the code clearly, and include a brief README explaining how to compile and run the ModelSim simulation from the command line.
The code must be synthesizable, but the only deliverables I need at this stage are:
• Verilog source files that realise the RMCM-based FIR
• A self-checking ModelSim test-bench with a small set of example input vectors and expected outputs
• Simulation snapshots or log files that prove the filter’s impulse response and steady-state behaviour match the theoretical values
If the design is parameterisable (tap count, word-length, coefficient set) that will make later hardware migration easier, but it is optional—clarity and correctness take priority.
Please keep the directory tree simple, comment the code clearly, and include a brief README explaining how to compile and run the ModelSim simulation from the command line.