Electrical Engineer Required -- 4
Budget: $30 – $250 USD
Draw the schematic for each gate and its size assuming you use complementary CMOS logic for the circuit
implementation and assuming a minimum size inverter of (W/L)n=2, (W/L)p=4
Calculate the overall propagation delay from input “C” to output “Out1” to output (i.e. use the minimum size inverter as
reference for the calculation)
If you were to implement the above circuit using dynamic logic, draw the resulting circuit schematic for one path (i.e.
from A to Out1) what is the low to high propagation delay of the circuit?
implementation and assuming a minimum size inverter of (W/L)n=2, (W/L)p=4
Calculate the overall propagation delay from input “C” to output “Out1” to output (i.e. use the minimum size inverter as
reference for the calculation)
If you were to implement the above circuit using dynamic logic, draw the resulting circuit schematic for one path (i.e.
from A to Out1) what is the low to high propagation delay of the circuit?
Related categories:
Electronics
Electrical Engineering
Circuit Design
Electronic Design
Digital Electronics