64-bit FPGA Pulse Counter
Budget: ₹1,500 – ₹12,500 INR
I have to count very fast digital pulses—up to 200 MHz—using a Xilinx XC7S50 (Spartan-7, BGA package). The design must implement four independent 64-bit counters that share a common asynchronous reset line brought out to a single input pin. Read-back of the counts will happen over an SPI link, so the HDL should expose a simple, register-mapped SPI slave.
Alongside the synthesizable VHDL or Verilog, I also need practical guidance on the hardware: how to lay out or select a compact development board that suits the XC7S50, ensures the 200 MHz signal integrity, and brings out the reset and SPI pins cleanly. If an off-the-shelf board will work, point me to it; if a custom carrier is wiser, outline the critical constraints (clocking, decoupling, pin assignments, oscillator choice, etc.).
Deliverables
• Synthesizable HDL for the four 64-bit pulse counters with reset and SPI interface
• XDC constraints ready for Spartan-7 speed-grade selection
• Self-checking test-bench exercising 200 MHz edge cases
• Brief hardware guideline or schematic snippet covering clock source, I/O standards, and pinout
• Short read-me explaining build flow in Vivado and the register map for SPI access
Everything must compile without timing violations in Vivado and be ready for on-board verification.
Alongside the synthesizable VHDL or Verilog, I also need practical guidance on the hardware: how to lay out or select a compact development board that suits the XC7S50, ensures the 200 MHz signal integrity, and brings out the reset and SPI pins cleanly. If an off-the-shelf board will work, point me to it; if a custom carrier is wiser, outline the critical constraints (clocking, decoupling, pin assignments, oscillator choice, etc.).
Deliverables
• Synthesizable HDL for the four 64-bit pulse counters with reset and SPI interface
• XDC constraints ready for Spartan-7 speed-grade selection
• Self-checking test-bench exercising 200 MHz edge cases
• Brief hardware guideline or schematic snippet covering clock source, I/O standards, and pinout
• Short read-me explaining build flow in Vivado and the register map for SPI access
Everything must compile without timing violations in Vivado and be ready for on-board verification.