Verilog 1011 FSM for Zynq

I need a concise, synthesizable Verilog finite-state machine that detects the bit sequence 1011 (with overlap) and drives a single-cycle “found” pulse when the pattern appears. The design must target a Xilinx Zynq board and be built in Vivado 2022.1. Please use binary state encoding; that choice is fixed for this job.

Here’s how I’d like the work delivered:

• Source files: top-level Verilog module, separate testbench, and any support files.
• Constraints: an XDC pinout I can adapt to my board.
• Vivado 2022.1 project archive, including synthesis and implementation reports.
• Generated .bit file so I can program the FPGA immediately.
• Short read-me explaining the state-transition diagram, how overlap is handled, and how to reproduce the build in Vivado.

Acceptance is based on simulation waveforms showing correct detection, no timing violations after implementation, and successful programming of my Zynq board with the supplied bitstream.