VLSI Logic-to-Layout Final Assignment Assistance

Title: Need Help Completing VLSI Logic-to-Layout Final Assignment (Coursera – Part 1 & 2)
Description:

Hi,
I’m currently working on the final assignments for the VLSI: Logic to Layout (Part 1 & 2) course on Coursera, and I’m really struggling to complete them. I am looking for someone who has strong experience in digital logic design, VLSI flow, Boolean functions, PCN format, Unate Recursive Complement, BDDs, logic optimization, and possibly simple C/C++ implementation.

The assignment involves:
• Working with Boolean functions and PCN representations
• Running/implementing Unate Recursive Complement (URC)
• Understanding logic synthesis concepts from SIS
• Possibly helping debug or complete C/C++ code used for the assignment
• Guiding me through the steps or helping generate the correct output files for submission
Understand the VLSI logic-to-layout concepts taught in the course
Help me complete the required outputs correctly
Work with me immediately (preferably today)

If you have a background in VLSI, digital design, logic synthesis, or EDA tools, please reach out.
Thanks!