SystemVerilog RISC-V FPGA Implementation

I am working on Experiment 4 for a RISC-V datapath design using SystemVerilog in Xilinx Vivado (simulation only).

The project requires implementing the following RTL modules from scratch according to the RISC-V ISA specification:

1. IMMED_GEN
This module must generate all five RISC-V immediate formats from instruction register bits [31:7]:

• I-type
• S-type
• B-type
• U-type
• J-type

Each immediate must be correctly sign-extended and aligned according to the official RISC-V bit-field definitions.

2. BRANCH_ADDR_GEN
This module must compute the target addresses for:

• JAL
• JALR
• Conditional branch instructions

by adding the appropriate immediate value to the base PC value and ensuring correct address alignment.

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CURRENT ISSUE:

My previous implementation has incorrect immediate values due to sign-extension and bit-placement errors across multiple instruction formats (especially B-type). The simulation waveform has been marked incorrect by the instructor.

At this point I am looking to fully re-implement both modules in synthesizable RTL to ensure:

• correct immediate bit extraction
• proper sign-extension
• correct left-shifting/alignment for branch and jump formats
• accurate JAL/JALR/branch target address computation
• waveform output matches expected RISC-V behavior

Simulation must produce correct immediate outputs for all instruction types.

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TOOLS / REQUIREMENTS:

• Xilinx Vivado
• SystemVerilog
• RTL design experience
• Familiarity with RISC-V instruction encoding

I can provide:

• assignment instructions
• testbench
• expected immediate values
• waveform reference
If you do well and the rates are reasonable I have many projects that I need to do and will hit you up directly for those as well