Simple FPGA VHDL Design
Budget: $10 – $30 USD
I need clean, well-documented VHDL that implements a set of simple digital circuits on an FPGA. The task sits firmly in the Digital circuits design space—no signal-processing tricks or embedded firmware layers—just straightforward gate-level logic and a few flip-flops brought to life in hardware.
Here is what I expect:
• VHDL source files for each module
• A small, self-checking testbench that runs in ModelSim/Questa or an equivalent simulator
• Clear synthesis-ready code that fits easily onto a mid-range Xilinx or Intel development board (the exact board can be generic; resources should stay minimal)
• A short README outlining how to simulate, synthesize, and pin-map the design
Because the scope is intentionally simple, I value concise code, sensible naming conventions, and comments that make the intent obvious at first glance. If you can deliver in a day or two, even better—just let me know your timeline when you bid.
Here is what I expect:
• VHDL source files for each module
• A small, self-checking testbench that runs in ModelSim/Questa or an equivalent simulator
• Clear synthesis-ready code that fits easily onto a mid-range Xilinx or Intel development board (the exact board can be generic; resources should stay minimal)
• A short README outlining how to simulate, synthesize, and pin-map the design
Because the scope is intentionally simple, I value concise code, sensible naming conventions, and comments that make the intent obvious at first glance. If you can deliver in a day or two, even better—just let me know your timeline when you bid.