Multiplexer & Demux Circuit Design-tutor needed

I’m working through the combinational-circuits portion of my digital design course and need hands-on support to design and fully implement multiplexers and demultiplexers. The goal is to move from logic-level concepts all the way to a working circuit that can be demonstrated in the lab.

Here is what I’d like from you:

• A clear derivation of the truth tables, Boolean expressions, and any Karnaugh-map (or equivalent) minimisation that leads to the final gate-level schematic.
• An HDL version of the same circuit (Verilog or VHDL—whichever you prefer) that compiles cleanly and is ready for simulation.
• Simulation results that verify correct operation for every input combination; ModelSim, Vivado, Quartus, or Logisim waveforms are all acceptable.
• Brief, well-commented documentation so I can present the design during our tutorial session and explain each decision made along the way.

If you see opportunities to streamline logic or suggest alternative gate technologies (TTL, CMOS, FPGA primitives), feel free to include them—learning the optimisation process is part of the exercise. Once we’re confident in simulation, I’ll move the design onto a small FPGA board for the laboratory component, so pin assignments or constraint files would be a welcome bonus.

Deliver everything as a zip containing the schematic/HDL files, simulation testbench, resulting waveforms, and a concise PDF report. I’m ready to get started right away and will be responsive to questions so we can iterate quickly.