Low Power MBE Design in Virtuoso -- 2
Budget: ₹600 – ₹1,500 INR
The work centres on translating the “Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style” into a genuinely new Modified Booth Encoder built in Cadence Virtuoso for a 90 nm CMOS process. Power efficiency is my primary concern; I need to see a measured Power-Delay-Product improvement of between 10 % and 20 % over both the conventional and the original PTL-based implementations discussed in the paper, without incurring unacceptable timing or area penalties.
You will be working inside Virtuoso’s Schematic Editor for the design entry, Spectre for all functional and corner simulations, and Virtuoso Layout Suite to demonstrate layout feasibility and extract accurate parasitics. The final intent is a journal-ready set of results, so every figure and table must be reproducible from the project files you provide.
Deliverables
• Complete schematic hierarchy, properly annotated
• Spectre test-bench setup covering typical, slow, and fast PVT corners
• Timing and power waveforms with clearly marked measurement points
• Tabulated comparison of power, delay, and PDP against the two baseline MBE designs
• Brief design-choice report that justifies your logic style, transistor sizing, and any gating or clocking techniques used
• GDSII or at minimum a DRC-clean layout view plus extracted netlist showing the same PDP improvement
Acceptance is contingent on a verified 10 %–20 % PDP reduction when the extracted view is simulated under the same conditions applied to the reference designs.
You will be working inside Virtuoso’s Schematic Editor for the design entry, Spectre for all functional and corner simulations, and Virtuoso Layout Suite to demonstrate layout feasibility and extract accurate parasitics. The final intent is a journal-ready set of results, so every figure and table must be reproducible from the project files you provide.
Deliverables
• Complete schematic hierarchy, properly annotated
• Spectre test-bench setup covering typical, slow, and fast PVT corners
• Timing and power waveforms with clearly marked measurement points
• Tabulated comparison of power, delay, and PDP against the two baseline MBE designs
• Brief design-choice report that justifies your logic style, transistor sizing, and any gating or clocking techniques used
• GDSII or at minimum a DRC-clean layout view plus extracted netlist showing the same PDP improvement
Acceptance is contingent on a verified 10 %–20 % PDP reduction when the extracted view is simulated under the same conditions applied to the reference designs.