Logisim 32-bit RISC Pipeline Design

I need a complete Logisim circuit that realises a 32-bit RISC processor whose instruction width is 16 bits. The core must follow the classic five-stage pipeline—Fetch, Decode, Execute, Memory, Writeback—and run smoothly at one instruction per cycle once the pipe is filled.

Key points to observe
• The datapath and control should be entirely built in Logisim (standard edition is fine).
• Branch prediction is required; a simple one-bit or two-bit predictor is acceptable as long as it is integrated in the Fetch stage and demonstrably improves flow.
• Forwarding and hazard detection units are not needed unless you decide they simplify your solution, but the design must avoid structural or data hazards that would break correct program execution.
• Instruction memory, register file, ALU, data memory and any auxiliary structures must work with 32-bit data while accepting 16-bit encoded instructions. Feel free to choose your own instruction format as long as you document it clearly.

Deliverables
1. The .circ Logisim file with a clean, labelled schematic.
2. A brief PDF or Markdown write-up explaining the instruction set, pipeline timing, branch predictor operation and a short test program that proves correct execution across all stages.

I will verify the design by loading the circuit in Logisim, single-stepping through your supplied program and checking that the predicted vs. actual branch decisions match your documentation.